Method and system for power distribution analysis

ABSTRACT

Disclosed are systems and methods for electrical verification of integrated circuits. Methodologies are described for verification of the power and ground distribution systems (PDS) for system-on-a-chip (SoC) and the verification of the interaction of the PDS with the behavior of integrated circuits.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No.60/652,919 filed Feb. 14, 2005, which is hereby incorporated byreference in its entirety.

COPYRIGHT NOTICE

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BACKGROUND AND SUMMARY

The present invention relates to power integrity verification forelectrical designs. In particular, embodiments of the present inventionprovide methods, systems, and methodologies to validate electricalcharacteristics of power distribution systems (PDSs) in electrical(e.g., IC chip) designs. This type of verification can, for example,ensure that each cell and transistor in the design receive sufficientvoltage to operate functionally correct.

Some embodiments of the invention provide a methodology, method, andsystem for multi-level hierarchical, vector-independent dynamicverification of PDS in Systems on Integrated Circuit orSystems-on-a-Chip (hereinafter SoC) with transistor level resolution.Examples of SoC include small electronic devices made out ofsemiconductor materials which contain various functional components suchas memory, digital and analog blocks made out of passive and activeelectronic devices. Examples of PDS include physical wiring composed ofelectrical conductive segments providing electrical connection betweenthe pins of a SoC to all active and passive devices on a SoC.

Examples of systems and methods having multi-level hierarchicalverification include systems and methods having the ability to validatethe PDS for a cell, macro, or block of a SoC, to extract the physicaland electrical characteristic of the cell, macro or block, and togenerate a model. Such a model is defined as a PDS model. A PDS modelcan be used for the verification of PDS at the next hierarchy level. Thenext hierarchy level can be a macro, a block, or the complete SoC. Thismethodology is called the bottom-up multi-level hierarchicalverification.

Other examples for multi-level hierarchical verification include systemsand methods having the ability to perform PDS verification at a specifichierarchy level using PDS models and to capture boundary conditions foreach component described by a PDS model and used in the hierarchicallevels of investigation. The captured boundary conditions can than beused for PDS verification at a lower hierarchical level. Thismethodology is called the top-down multi-level hierarchicalverification.

Dynamic verification of PDS in SoC includes, for example, the capabilityto calculate the time-dependent voltages and currents for all segmentsof PDS. Static verification of PDS in SoC includes, for example, thecapability to calculate the time-independent (also called average orpeak) voltages and currents for all segments of PDS.

Vector-independent dynamic verification of PDS in SoC includes, forexample, the capability to calculate the time-dependent power or currentconsumption of the components of a SoC independent of functional stimulifor the components of a SoC. Transistor level resolution includes, forexample, the ability to calculate the time-dependent fluctuations of thevoltages at all segments of PDS from the external connections of the SoC(power and ground pins) through all wire segments of PDS to terminals toactive and passive semiconductor devices such as transistors andcapacitors for all types of components of SoC.

Prior approaches for implementing power distribution analysis all suffersignificant functional drawbacks. For example, systems that performdynamic verification at transistor level require user providedfunctional stimuli to calculate the time-dependent current consumption.Moreover, systems that perform dynamic verification at transistor orgate level do not allow for multi-level hierarchical PDS verification.Systems that perform dynamic verification at gate level also requireeither user provided definitions of switching probabilities for eachsignal net between the components of SoC or user provided functionalstimuli for primary inputs of the SoC or the components thereof.Furthermore, vector-independent dynamic verification at gate level doesnot provide transistor level resolution for PDS verification. Inaddition, prior approaches also lack the ability to calculate realisticapproximation of worst-case time-dependent current consumption for SoCwithout user specified power constraints. Finally, prior approaches alsolack means for sending effective feedback to the users about theelectrical characteristic of PDS and decoupling capacitors.

Some embodiments of the present invention overcomes the limitations ofprior solutions by enabling dynamic verification at the gate levelrequiring neither user provided definitions of switching probabilitiesfor each signal net between the components of SoC nor user providedfunctional stimuli for primary inputs of SoC as well as a statisticalapproach to determine locally simultaneously switching components andcreating worst case voltage fluctuations. Some embodiments of theinstant invention are directed to both a dynamic top-down and a dynamicbottom-up multi-level hierarchical PDS verification with transistorlevel resolution. In addition, some embodiments of the present inventionteach a vector-independent dynamic verification at gate level withtransistor level resolution for PDS verification and enable the use ofstatic PDS verification techniques to build PDS models for components ofSoC and the use of these models for multi-level hierarchical dynamic PDSverification. Furthermore, some embodiments of the instant inventionprovide a methodology to measure the effectiveness of explicitdecoupling capacitors for placement optimization as well as graphicalrepresentation. In addition, some embodiments of the present inventionteach a methodology to take into account the variation of the electricalcircuit behavior due to manufacturing process variations for thevector-independent calculation of current consumption for SoC.

Further details of aspects, objects, and advantages of the invention aredescribed below in the detailed description, drawings, and claims. Boththe foregoing general description and the following detailed descriptionare exemplary and explanatory, and are not intended to be limiting as tothe scope of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention and, together with the DetailedDescription, to serve to explain the principles of the invention.

FIG. 1 illustrates an embodiment of an PDS model.

FIG. 2 shows a time-dependent current consumption waveform.

FIG. 3 shows a flow for performing vector-independent calculation oftime-dependent instance based current consumption data flow according tosome embodiments of the invention.

FIG. 4 shows a PDS Verification Flow according to some embodiments ofthe invention.

FIG. 5 describes transistor level PDS verification according to someembodiments of the invention.

FIG. 6 describes cell-based PDS verification according to someembodiments of the invention.

FIG. 7 shows a flow for PDS verification output processing according tosome embodiments of the invention.

FIG. 8 shows decoupling capacitor effectiveness graphical representationdata and process flow according to some embodiments of the invention.

FIG. 9 shows a decoupling capacitor aware placement optimization flowaccording to some embodiments of the invention.

FIG. 10 illustrates an example computing architecture with which theinvention may be implemented.

DETAILED DESCRIPTION

Embodiments of the present invention provide methods, systems, andmethodologies to validate electrical characteristics of powerdistribution systems (PDSs) in an electrical (e.g., IC chip) designs. Asnoted above, some embodiments of the invention provide avector-independent methodology, method, and system for multi-levelhierarchical, dynamic verification of PDS in Systems on IntegratedCircuit (SoC) with transistor level resolution. Some embodiments of theinvention contain several components which are described in thefollowing description.

PDS Model

One of the purpose of the PDS models is to capture the physical as wellas electrical characteristics of the PDS to serve, for example, as thebasis for multi-level, hierarchical PDS verification. The PDS modelcaptures the information used for PDS verification as well astime-varying, vector-independent gate level current consumptioncalculation. Both components facilitate multi-level hierarchical PDSverification, both in the bottom-up and the top-down approach.Additionally, this enables embodiments of the invention to measure,report, and optimize the effectiveness of decoupling capacitors asintegral part of PDS.

According to one embodiment of the present invention, a PDS modelcomprises some or all of the following information for a component asshown in FIG. 1 and described below:

Physical information 102 about the segments of PDS used to connect thecomponent within a SoC. These sets of segments are usually referred asports of a component, and the physical information includes size,location, and layer information.

For each segment a terminal point is determined, which further definesthe connection of the electrical model for a component.

An electrical network 104 describing the electrical characteristics ofthe PDS internal to the component. The electrical model can be as simpleas a parasitic resistor network and is connected to the terminal pointsof the PDS model. Moreover, the parasitic network can be described byone or more RLC model or one or more subsets thereof. The electricalmodel can also be directly extracted from the layout information of theinternal PDS. Furthermore, the size of the electrical model can bedecreased by applying network reduction techniques.

Location of current sinks 106. Current sinks are in general active orpassive electrical devices which are consuming current due to activeoperation or leakage through the semiconductor devices.

An electrical model 108 for the current sinks within the component. Anelectrical model can be as simple as a constant or a time-dependentcurrent source. The model can also be described as a function of thesupply voltages and the electrical environment of the component. Themodel can describe the absolute current for each sink or relativecurrent strength between the sinks in a component.

Netlist connectivity information 110. The netlist connectivityinformation can be at the transistor level or an abstraction thereof.The netlist connectivity information includes as well electrical modelsdescribing the electrical behavior of the signal interconnect betweencomponents of the netlist. The electrical model can be as simple as acapacitor describing the parasitic signal net capacitor.

Vector-Independent Calculation of the Time-Dependent Gate Level CurrentConsumption

The problem being addressed by a vector-independent calculation of thetime-dependent gate level current consumption methodology is tocalculate the switching situation which causes the worst-case transientIR drop without the need to perform functional verification, i.e., todetermine which components are switching simultaneously at which pointin time in which direction based on design constraints used for andresults of static timing analysis. An example of a vector-independentcalculation is a calculation that is performed in a vector-less manner.An example time-dependent gate level current consumption waveform isshown in FIG. 2.

Other proposed approaches are focused solely on the determination of theworst case or peak power consumption and its associated transientcurrent consumption waveform. While the knowledge of the peak powerconsumption waveform is certainly a good measure, it doesn't necessarilycorrelate with current consumption waveform causing the worst-casttransient IR drop.

For example, one proposed approach is a methodology to calculate the socalled switching scenarios, i.e. to calculate which component isswitching at which time and in which direction. The calculation in thisapproach is based on the timing window calculated by static timinganalysis, the transition density under consideration of local logicsatisfiability as well as under peak-average ratio constraints. Whilethe proposed methodology can be used to calculate switching situations,the approach does not provide the ability to determine the transientpeak power consumption. Therefore a peak-average ratio constraint isintroduced as an artificial constraint to mask the deficiency of theproposed methodology. It can be easily shown that the peak-average ratiovaries for different SoC as well as between different blocks of a SoC.More importantly, the method does not take into account the impact oflocally simultaneously switching components causing large voltagefluctuations.

In other proposed approaches, genetic algorithms are used to calculateworst case vector sets within a given confidence range based on seedsequence(s) in combination with gate level functional simulationalgorithms. One drawback of this methodology is that seed sequence needsto be provided by the user of the system, the choice of the seedsequence has strong impact on the convergence behavior of the proposedmethodology. Moreover, several, usually resource intensive, functionalverification cycles are required until a vector sequence approximatingthe worst case situation is determined in the defined confidence range.In addition, this approach is only applicable to calculate theworst-case power consumption, and is therefore not applicable todetermine the worst-case transient IR drop.

Some embodiments of the present invention include a methodology thatprovides the ability to calculate realistic time-dependent currentconsumption to approximate the worst-case impact on the powerdistribution system. As shown in the flowchart of FIG. 3, the time anddirection of the switching of each individual component 300 iscalculated based on a time-dependent simultaneous switching probabilityfunction P_(SSO)(t) 310. The time-dependent simultaneous switchingprobability function P_(SSO)(t) 310 is calculated based on the switchingcurrent signature 308, the timing probability P_(T)(t) 302, thenormalized transition density P_(TD) 304, normalized IR probabilityP_(IR) 306, which are described in further details in the subsequentparagraphs.

One component of the time-dependent simultaneous switching probabilityfunction is the timing probability P_(T)(t) 302, e.g. the probabilitythat a specific instance will switch in a certain direction at specificpoint in time. One approach is to define the timing probability 302 asan uniform distribution function with P_(T)(t)=1 within the timingwindow and P_(T)(t)=0 outside. However, discrete switching time pointsare calculated during static timing analysis, and this information canbe used to model the timing probability function 302 more realistically.In addition, statistical static timing analysis will enable theconsideration of switching time variations due to process variations.The concept of timing probabilities P_(T)(t) 302 used in this inventionis the basis to take the process variations into account for thevector-independent calculation of the current consumption 300.

Another component of the time-dependent simultaneous switchingprobability function is the normalized transition density P_(TD) 304,which can be calculated based on the actual transition density for agiven signal net, derived either from functional simulation or throughprobabilistic propagation or a combination thereof, as described in“Full-chip vector-less dynamic power integrity analysis and verificationagainst 100 uV/100 ps-resolution measurement”, Custom IntegratedCircuits Conference, 2004. Proceedings of the IEEE 2004, 3-6 Oct. 2004,which is hereby incorporated by reference in its entirety.

Another component of the time-dependent simultaneous switchingprobability function is the normalized IR probability P_(IR) 306, i.e.,sensitivity of voltage fluctuation versus load current changes based onthe resistive network representing DC characteristic of the PDS. Thesensitivity of voltage fluctuations may include statistical variation ofthe DC characteristic caused by the process variation, and eachparasitic resistive element is described by a mean value anddistribution function. Therefore, the time-dependent simultaneousswitching probability function P_(SSO)(t) 310 can be expressed in thefollowing equation:P _(SSO)(t)=f(P _(T)(t),P _(TD) ,P _(IR)))  Equation 1

Stochastic techniques such as the Monte-Carlo method based on thetime-dependent simultaneous switching probability P_(SSO)(t) 310 areused together with the switching current waveform for each individualinstance to calculate the time dependent current consumption acrossmultiple clock cycles.

Multi-Level Hierarchical Bottom-Up And Top-Down PDS Verification

FIG. 4 shows the basic PDS verification flow according to an embodimentof the invention. In this flow, the design data 402 provide the inputdata into the PDS verification system 404 (which comprises transistorlevel PDS verification system 408 and cell-based PDS verification system410 described in more detail with respect to FIGS. 5 and 6), followed byprocessing of generated output data 406.

The PDS verification methodology can be applied to complete or partialdesign data 402. The design data 402 in one embodiment of the inventioninclude some or all of the following information such as the designlayout information, the cell library information, the environmentconstraints and models, and/or pre-extracted layout parasitic data.Moreover, the cell library information may comprise information such asthe timing libraries, the power libraries, the PDS model libraries, thephysical abstractions, and/or the transistor level description of cellcontents. Finally, the environment constraints and models may compriseinformation such as the SoC package model data, the design operationconstraints, and/or the PDS boundary conditions.

The transistor level PDS verification system 408 is described in furtherdetails in FIG. 5 and enables PDS verification at the transistor level.The transistor level PDS verification system 408 can be applied toverification and characterization of standard cells, I/O cells, analog,digital, and mixed signal custom design blocks. Furthermore, FIG. 5shows the complete transistor level PDS verification system 408, andsimplifications are possible to reduce the amount of data to be analyzedas well as captured in the PDS models. The cell-based PDS verificationsystem 410 is described in further details in FIG. 6.

Referring to FIG. 5, the transistor level PDS verification system 408performs the transistor level PDS verification 508 based upon the inputof the design data 402. The PDS verification results are furtherprocessed in the PDS verification output processing 406. In addition, insome embodiments of the present invention, the transistor level PDSverification system further performs the transistor level parasiticextraction 504 and one or more transistor level circuit analyses 506 toachieve the desired transistor level accuracy.

FIG. 6 shows the cell-based PDS verification system 410 in oneembodiment of the invention. In this cell-based PDS verification 410,the design data 402 provide the input data into the cell-based PDSverification system 410. This flow is typically applied to designs andblocks generated by place & route tools. The steps of cell-basedparasitic extraction 604 and the cell-based static and/or time-dependentpower consumption calculation 608 are performed at the cell level andtherefore, this flow can be referred to as cell based PDS verification.Moreover, transistor level accuracy is achieved by merging the contentsof PDS models for the cells with the parasitic data 606 generated instep 604 and 608. The results of the cell based PDS verification will befurther processed in 406 of the PDS verification flow. The PDSverification output processing 406 contains the PDS model generation ofthe block or chip verified. FIG. 7 further describe the PDS verificationoutput in more details.

Referring to FIG. 7. The PDS verification output processing phase 406contains the generation of user consumable data and PDS verificationresults 704 as well as the consolidation of verification output, datacompression, and data processing to build PDS models for the cell orblock analyzed 706 with the transistor level PDS verification system408. The consolidated verification output, the PDS model generated, andcompressed data in 706 may be further utilized to merge with the PDSmodel library 708 or to establish the instance based boundary conditions710.

The PDS model generated in this step can then be used at the next designhierarchical level to represent a block or partition within a specificdesign hierarchy level up to the complete SoC. The methodologies ofemploying the transistor level PDS verification system 408 and thecell-based PDS verification system 410 enable a bottom-up multi-levelhierarchical PDS verification.

Top-down PDS verification is enabled with the methodology describedherein by capturing PDS boundary conditions 710 for individual designinstances. A design instance can be, for example, a partition, a block,a macro, or a cell. The instance based boundary conditions 710 areconsidered as environment constraints as part of the design data and canbe applied at various hierarchical levels. The instance specific PDSboundary conditions 710 enable a methodology to perform PDS verificationon a specific design instance taking into account the interactionbetween different design instances without having to perform PDSverification on the complete SoC. This methodology can be referred to asthe top-down PDS verification.

Decoupling Capacitor Effectiveness and Graphical Representation ofDecoupling Capacitor Effectiveness

Textual and numerical data are used to analyze the results of PDSverification in detail. However, due to the amount of data to be handledduring block and full-chip PDS validation, this it is not an efficientway to provide insight about the characteristics of the PDS from aglobal perspective. Some embodiments of the invention provide agraphical approach to provide feedback about the effectiveness ofdecoupling capacitors from a global perspective. A global perspective isimportant in understanding the effectiveness of explicit decouplingcapacitors under consideration of parasitic, embedded, and naturaldecoupling capacitors as well as in allowing the optimization of theplacement of explicit decoupling capacitors.

Referring to FIG. 8, one of the purposes of using explicit decouplingcapacitors in a PDS is to stabilize the local supply voltages forindividual instances in order to minimize device switching delayvariations or to avoid functional failures due to the collapse of thesupply voltages. The effectiveness of decoupling capacitors 806 cantherefore be measured as the ratio of the device switching delayvariation Δτ 802 due to transient PDS variations versus the deviceswitching delay τ 804 at local supply voltages determined by static PDSvalidation. As the switching delay is a function of the local supplyvoltages during the switching event, the effectiveness of explicitdecoupling capacitors can therefore be approximated as a function of theratio of the transient supply voltage variation vs. the static supplyvoltage at the switching cells:I=f(Δτ,τ)≈f(ΔV(t),ΔV _(s))  Equation 2

Furthermore, in one embodiment of the present invention, a developedmethodology includes the mapping of the effectiveness of explicitdecoupling capacitor, I, into a color index 808 as shown in FIG. 8. Thecolor index for each cell may compose, for example, a thermal map, whichprovides an efficient way to represent the effectiveness of decouplingcapacitors globally.

Optimization of the Placement of Decoupling Capacitors

In one embodiment of the instant invention, the developed methodology tomeasure the effectiveness of explicit decoupling capacitors as definedin Equation 2 can be used as well as cost function together withplacement optimization techniques during the placement optimization ofexplicit decoupling capacitors:Φ′=Φ+ΣI ²  Equation 3

Φ is the original placement optimization cost function, Φ′ is themodified cost function capturing the effectiveness of decouplingcapacitors. An embodiment of a decoupling capacitor aware optimizationmethodology is shown in FIG. 9. The optimization cost function Φ 904 forthe initial instance placement 902 is first calculated; then themodified optimization cost function Φ′ 906 is evaluated by taking intoaccount the effectiveness of decoupling capacitors. This embodiment ofthe invention further defines a threshold value for a convergencecriterion and determines whether the convergence criterion is met in910. If the convergence criterion is met the current placement is thusdetermined to be the final placement 912. If the convergence criterionis not met this embodiment of the invention, calculates new placementand its associated optimization cost function Φ′, and repeat the aboveiterative process until the convergence criterion is met in 910.

System Architecture Overview

FIG. 10 is a block diagram of an illustrative computing system 1400suitable for implementing an embodiment of the present invention.Computer system 1400 includes a bus 1406 or other communicationmechanism for communicating information, which interconnects subsystemsand devices, such as processor 1407, system memory 1408 (e.g., RAM),static storage device 1409 (e.g., ROM), disk drive 1410 (e.g., magneticor optical), communication interface 1414 (e.g., modem or Ethernetcard), display 1411 (e.g., CRT or LCD), input device 1412 (e.g.,keyboard), and cursor control.

According to one embodiment of the invention, computer system 1400performs specific operations by processor 1407 executing one or moresequences of one or more instructions contained in system memory 1408.Such instructions may be read into system memory 1408 from anothercomputer readable/usable medium, such as static storage device 1409 ordisk drive 1410. In alternative embodiments, hard-wired circuitry may beused in place of or in combination with software instructions toimplement the invention. Thus, embodiments of the invention are notlimited to any specific combination of hardware circuitry and/orsoftware. In one embodiment, the term “logic” shall mean any combinationof software or hardware that is used to implement all or part of theinvention.

The term “computer readable storage medium” or “computer usable storagemedium” as used herein refers to any medium that participates inproviding instructions to processor 1407 for execution. Such a mediummay take many forms, including but not limited to non-volatile media andvolatile media. Non-volatile media includes, for example, optical ormagnetic disks, such as disk drive 1410. Volatile media includes dynamicmemory, such as system memory 1408.

Common forms of computer readable media includes, for example, floppydisk, flexible disk, hard disk, magnetic tape, any other magneticmedium, CD-ROM, any other optical medium, punch cards, paper tape, anyother physical medium with patterns of holes, RAM, PROM, EPROM,FLASH-EPROM, any other memory chip or cartridge, or any other mediumfrom which a computer can read.

In an embodiment of the invention, execution of the sequences ofinstructions to practice the invention is performed by a single computersystem 1400. According to other embodiments of the invention, two ormore computer systems 1400 coupled by communication link 1415 (e.g.,LAN, PTSN, or wireless network) may perform the sequence of instructionsrequired to practice the invention in coordination with one another.

Computer system 1400 may transmit and receive messages, data, andinstructions, including program, i.e., application code, throughcommunication link 1415 and communication interface 1414. Receivedprogram code may be executed by processor 1407 as it is received, and/orstored in disk drive 1410, or other non-volatile storage for laterexecution.

In the foregoing specification, the invention has been described withreference to specific embodiments thereof. It will, however, be evidentthat various modifications and changes may be made thereto withoutdeparting from the broader spirit and scope of the invention. Forexample, the above-described process flows are described with referenceto a particular ordering of process actions. However, the ordering ofmany of the described process actions may be changed without affectingthe scope or operation of the invention. The specification and drawingsare, accordingly, to be regarded in an illustrative rather thanrestrictive sense.

What is claimed is:
 1. A computer implemented, vector-independent methodfor calculating time-dependent current consumption, comprising: using atleast one processor that is programmed for performing: determining whichelectrical components are switching simultaneously at which point intime in which direction by calculating a time-dependent simultaneousswitching probability function; and calculating an instance specific,time-dependent current consumption by using at least a result of the actof calculating the time-dependent simultaneous switching probabilityfunction without performing functional verification to approximate aworst-case impact on a power distribution system, wherein the act ofcalculating the instance specific, time-dependent current consumptionprovides multi-hierarchical level verification with transistor levelresolution for an electronic circuit design, and the electronic circuitdesign comprises a plurality of hierarchical levels.
 2. The computerimplemented method of claim 1, in which the act of calculating thetime-dependent simultaneous switching probability function comprises:defining and calculating a timing probability; defining and calculatinga transition density; and defining and calculating a normalized IRprobability.
 3. The computer implemented method of claim 2, in which theact of defining and calculation said timing probability is based on oneor more discrete switching time points obtained from a static timinganalysis.
 4. The computer implemented method of claim 2, in which theact of defining and calculating said timing probability comprises takingswitching time variations due to process variations in account by usinga statistical timing analysis.
 5. The computer implemented method ofclaim 2, in which the act of defining and calculating said normalizedtransition density comprises defining and calculating an actualtransition density derived from a functional simulation or aprobabilistic propagation or a combination thereof.
 6. The computerimplemented method of claim 2, in which the act of defining andcalculating the normalized IR probability comprises: calculatingsensitivity of voltage fluctuation; and calculating load current changesbased on a resistive network representing a plurality of DCcharacteristics of said power distribution system.
 7. The computerimplemented method of claim 6, in which the sensitivity of voltagefluctuation of the calculation of said normalized IR probabilitycomprises one or more statistical variations of one or more DCcharacteristics caused by process variations.
 8. The computerimplemented method of claim 6, in which the resistive networkrepresenting a plurality of DC characteristics comprises one or moreparasitic resistive elements each of which being described by a meanvalue and a distribution function.
 9. The computer implemented method ofclaim 1, in which the act of determining which electrical components areswitching simultaneously at which point in time in which direction bycalculating a time-dependent simultaneous switching probability functionis based on one or more static timing analyses.
 10. The computerimplemented method of claim 1, in which the act of calculating theinstance specific, time-dependent current consumption further comprises:using a stochastic method based on said time-dependent simultaneousswitching probability calculating said time-dependent currentconsumption across multiple clock cycles; and using a switching currentwaveform for each of one or more individual instances.
 11. A computerprogram product that includes a computer usable storage medium having asequence of instructions which, when executed by at least one processor,causes the at least one processor to execute a process for calculatingrealistic, vector-independent, time-dependent current consumption, theprocess comprising: determining which electrical components areswitching simultaneously at which point in time in which direction bycalculating a time-dependent simultaneous switching probabilityfunction; and calculating a realistic, instance specific, time-dependentcurrent consumption by using a result of the act of calculating thetime-dependent simultaneous switching probability function withoutperforming functional verification to approximate a worst-case impact ona power distribution system, wherein the act of calculating the instancespecific, time-dependent current consumption provides multi-hierarchicallevel verification with transistor level resolution for an electroniccircuit design, and the electronic circuit design comprises a pluralityof hierarchical levels.
 12. The computer product of claim 11, in whichsaid sequence of instructions causes said processor to execute a processfor determining which electrical components are switching simultaneouslyat which point in time in which direction by calculating atime-dependent simultaneous switching probability function is based uponone or more static timing analyses.
 13. The computer program product ofclaim 11, in which the act of calculating the time-dependentsimultaneous switching probability function comprises: defining andcalculating a timing probability; defining and calculating a transitiondensity; and defining and calculating a normalized ER probability. 14.The computer program product of claim 13, in which the act of definingand calculating the normalized IR probability comprises: calculatingsensitivity of voltage fluctuation; and calculating load current changesbased on a resistive network representing a plurality of DCcharacteristics of said power distribution system.
 15. The computerprogram product of claim 11, in which the act of calculating theinstance specific, time-dependent current consumption further comprises:using a stochastic method based on said time-dependent simultaneousswitching probability calculating said time-dependent currentconsumption across multiple clock cycles; and using a switching currentwaveform for each of one or more individual instances.
 16. A system forcalculating realistic, vector-independent, time-dependent currentconsumption, comprising: a computer system which comprises at least oneprocessor and is programmed for performing: determining which electricalcomponents are switching simultaneously at which point in time in whichdirection by calculating a time-dependent simultaneous switchingprobability function; and calculating a realistic, instance specific,time-dependent current consumption by using a result of the act ofcalculating the time-dependent simultaneous switching probabilityfunction without performing functional verification to approximate aworst-case impact on a power distribution system, wherein the act ofcalculating the instance specific, time-dependent current consumptionprovides multi-hierarchical level verification with transistor levelresolution for an electronic circuit design, and the electronic circuitdesign comprises a plurality of hierarchical levels.
 17. The system ofclaim 16, in which the computer system that is programmed forcalculating the time-dependent simultaneous switching probabilityfunction is further programmed for performing: defining and calculatinga timing probability; defining and calculating a transition density; anddefining and calculating a normalized IR probability.
 18. The system ofclaim 17, in which the computer system that is programmed for definingand calculating the normalized IR probability is further programmed forperforming: calculating sensitivity of voltage fluctuation; andcalculating load current changes based on a resistive networkrepresenting a plurality of DC characteristics of said powerdistribution system.
 19. The system of claim 16, in which the computersystem is further programmed for performing: using a stochastic methodbased on said time-dependent simultaneous switching probabilitycalculating said time-dependent current consumption across multipleclock cycles; and using a switching current waveform for each of one ormore individual instances.